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? semiconductor components industries, llc, 2004 october, 2004 ? rev. 3 1 publication order number: ncp1201/d ncp1201 pwm current-mode controller for universal off-line supplies featuring low standby power with fault protection modes housed in soic?8 or pdip?8 package, the ncp1201 enhances the previous ncp1200 series by offering a reduced optocoupler current with additional brownout detection protection (bok). similarly, the circuit allows the implementation of complete off?line ac?dc adapters, battery chargers or switchmode power supplies (smps) where standby power is a key parameter. the ncp1201 features efficient protection circuitry. when in the presence of a fault (e.g. failed optocoupler, overcurrent condition, etc.) the control permanently disables the output pulses to avoid subsequent damage to the system. the ic only restarts when the user cycles the mains power supply. with the low power internal structure, operating at a fixed 60 or 100 khz, the controller supplies itself from the high?voltage rail, avoiding the need of an auxiliary winding. this feature naturally eases the designer's task in battery charger applications. finally, current?mode control provides an excellent audio?susceptibility and inherent pulse?by?pulse control. when the load current falls down to a pre?defined setpoint (v skip ) value, e.g. the output power demand diminishes, the ic automatically enters the skip cycle mode and can provide excellent efficiency under light load conditions. the skip mode is designed to operate at relatively lower peak current so that acoustic noise that commonly takes place will not happen with ncp1201. features ? pb?free packages are available ? ac line brownout detect protection, bok function ? latchoff mode fault protection ? no auxiliary winding operation ? internal output short?circuit protection ? extremely low no?load standby power ? current?mode with skip?cycle capability ? internal overtemperature shutdown ? internal leading edge blanking ? 250 ma gate peak current driving capability ? internally fixed switching frequency at 60 or 100 khz ? built?in frequency jittering for emi reduction ? direct optocoupler connection typical applications ? ac?dc adapters ? offline battery chargers ? auxiliary power supplies (usb, appliances, tvs, etc.) pdip?8 p suffix case 626 1 8 1 8 soic?8 d suffix case 751 18 5 3 4 (top view) bok cs hv pin connections 7 6 2 nc fb gnd drv vcc marking diagrams y = device code: 6 for 60 khz y = device code: 1 for 100 khz xx = device code: 60 for 60 khz xx = device code: 10 for 100 khz a = assembly location l = wafer lot y, yy = year w, ww = work week 201dy alyw 1201pxx awl yyww 1 8 see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information http://onsemi.com 1 8
ncp1201 http://onsemi.com 2 figure 1. typical application example ncp1201 u1 1 1 2 3 4 8 6 5 df06s br1 90 264 vac 1 2 + ? 4 3 c1 4.7 400 v + 470 h 0.2 a l1 c2 4.7 400 v + r1 195.7 k r2 4.3 k c3 470 p 250 v r3 100 k 1.0 w 1n4937 d1 q1 mtd1n60e + c4 10 f t1 d2 1n5819 47 h 1.0 a l3 6.5 v, 600 ma + c6 10 + + c5 10 c7 1.0 n 250 vac y1 1 2 4 3 u2 r4 2.7 0.5 w sfh6156?2 d3 470 h 0.2 a l2 5v1 * * please refer to the application information section.
ncp1201 http://onsemi.com 3 4 3 2 1 cs fb bok gnd drv v cc nc hv 8 7 6 5 figure 2. simplified functional block diagram 50 a i ref ? + output 80 k ? + ? + ? + output 1.07 v reset reset q set enable skip cycle comparator 60 or 100 khz clock oscillator ? + ? + + ? 10.5 v/12.5 v output internal regulator v ref overload startup blanking + ? output 250 ns l.e.b. 0.9 v 57 k 25 k + ? v ref 24 k maximum 83% duty cycle 250 ma ? + ? + 1.92 v + ? 20 k hv current source reset tsd
ncp1201 http://onsemi.com 4 pin function description pin no. pin name function description 1 bok bulk ok this pin detects the input line voltage by sensing the bulk capacitor, and disables the pwm when line voltage is lower than normal. 2 fb sets the peak current setpoint by connecting an optocoupler to this pin, the peak current setpoint is ad- justed according to the output power demand. internal monitoring of this pin level triggers the fault management circuitry. 3 cs current sense input this pin senses the primary inductor current and routes it to the internal comparator via an leb circuit. 4 gnd the ic ground ? 5 drv driving pulses the driver's output to an external mosfet. 6 vcc supplies the ic this pin is connected to an external bulk capacitor of typically 10 f. 7 nc no connection this unconnected pin ensures adequate creepage distance between high voltage pin to other pins. 8 hv generates the v cc from the line connected to the high?voltage rail, this pin injects a constant current into the v cc capacitor. maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit power supply voltage, pin 6 v cc ?0.3, 16 v input/output pins pins 1, 2, 3, 5 v io ?0.3, 6.5 v maximum voltage on pin 8 (hv) v hv 500 v thermal resistance, junction?to?air, pdip?8 version thermal resistance, junction?to?air, soic version r ja r ja 100 178 c/w c/w operating junction temperature range t j ?40 to +150 c operating ambient temperature range t a ?25 to +125 c storage temperature range t stg ?55 to +150 c esd capability, hbm (all pins except v cc and hv pins) (note 1) ? 2.0 kv esd capability, machine model (all pins except v cc and hv pins) (note 1) ? 200 v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: human body model (hbm) > 2.0 kv per jedec standard: jesd22?a114. machine model (mm) > 200 v per jedec standard: jesd22?a115. 2. latchup current maximum rating: 150 ma per jedec standard: jesd78.
ncp1201 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?25 c to +125 c, v cc = 11 v unless otherwise noted) characteristic symbol min typ max unit dynamic self?supply v cc increasing level at which the current source turns?off vcc off 11.5 12.5 13.5 v v cc decreasing level at which the current source turns?on vcc on 9.6 10.5 11.3 v internal ic current consumption, no output load on pin 5 i cc1 440 905 1300 a internal ic current consumption, 1.0 nf output load on pin 5 ncp1201p60, ncp1201d60 ncp1201p100, ncp1201d100 i cc2 0.75 1.6 1.6 2.1 2.2 2.8 ma internal ic current consumption, latchoff phase i cc3 405 575 772 a internal startup current source high?voltage current source at v ccon 0.2 v i c1 3.6 5.3 7.1 ma high?voltage current source at v cc = 0 v i c2 7.5 11.1 15 ma hv pin leakage current @ 450 v, v cc pin connected to ground i leak ? 30 70 a output section output voltage rise?time (cl = 1.0 nf, 10 v output) tr ? 116 ? ns output voltage fall?time (cl = 1.0 nf, 10 v output) tf ? 41 ? ns source resistance (v drv = ) r oh 26 38 60 sink resistance (v drv = ) r ol 4.0 10 22 current sense section (pin 5 unloaded) input bias current @ 1.0 v input level on pin 3 i ib?cs ? 10 100 na maximum current sense input threshold v ilimit 0.8 0.9 1.0 v default current sense threshold for skip cycle operation v ilskip 250 325 390 mv propagation delay from current detection to gate off state t del 35 65 160 ns leading edge blanking duration t leb 150 260 400 ns oscillator section (v cc = 11 v, pin 5 loaded by 1.0 k ) oscillation frequency ncp1201p60, ncp1201d60 ncp1201p100, ncp1201d100 f osc 52 92 60 100 72 117 khz built?in frequency jittering (as a function of vcc voltage) ncp1201p60, ncp1201d60 ncp1201p100, ncp1201d100 f jitter ? ? 493 822 ? ? hz/v maximum duty cycle d max 74 83 87 % feedback section (v cc = 11 v, pin 5 unloaded) internal pullup resistor r up 10 17 24 k feedback pin to pin 3 current setpoint division ratio i ratio 2.9 3.3 4.0 ? brownout detect section bok input threshold voltage v th 1.75 1.92 2.05 v bok input bias current (v bok < v th ) i ib?bok ? 11 100 na source bias current (turn on after v bok > v th ) i sc 40 50 58 a frequency skip cycle section built?in frequency skip cycle comparator voltage threshold v skip 0.96 1.07 1.18 v thermal shutdown thermal shutdown trip point, temperature rising (note 3) t sd ? 145 ? c thermal shutdown hysteresis t hyst ? 25 ? c 3. verified by design.
ncp1201 http://onsemi.com 6 typical characteristics t j , junction temperature ( c) 125 100 75 50 25 0 ?25 12.9 vcc off , v cc off threshold voltage (v) 12.5 12.3 11.9 11.7 12.1 12.7 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 1100 i cc1 , current consumption with no load ( a) 1000 800 700 600 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 2.6 i cc2 , current consumption (ma) 2.2 2.0 1.6 1.4 1.8 2.4 900 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 8.0 i c1 , hv pin startup current source (ma) 5.0 3.5 2.0 0.5 6.5 v cc = 11 v 1 nf load figure 3. v cc off threshold voltage vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 10.8 vcc on , v cc on threshold voltage (v) 10.2 10 9.8 10.4 10.6 figure 4. v cc on threshold voltage vs. junction temperature figure 5. ic current consumption, i cc1 vs. junction temperature figure 6. ic current consumption, i cc2 vs. junction temperature figure 7. ic current consumption at latchoff phase vs. junction temperature figure 8. hv pin startup current source vs. junction temperature 100 khz 60 khz t j , junction temperature ( c) 125 100 75 50 25 0 ?25 700 i cc3 , ic current consumption at latchoff phase ( a) 600 500 400 300
ncp1201 http://onsemi.com 7 typical characteristics figure 9. hv pin startup current source vs. junction temperature figure 10. leakage current vs. junction temperature figure 11. output source resistance vs. junction temperature figure 12. output sink resistance vs. junction temperature figure 13. cs pin input bias current @ 1.0 v vs. junction temperature figure 14. maximum current sense threshold vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 12 i ib?cs , cs pin input bias current (na) 10 9 7 6 8 11 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 70 r oh , source resistance ( ) 60 40 30 0 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 20 r ol , sink resistance ( ) 16 12 4 0 8 50 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 1.00 v ilimit , maximum current sense threshold (v) 0.96 0.88 0.84 0.80 0.92 20 10 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 14 i c2 , hv pin startup current source (ma) 12 8 6 4 10 v cc = 0 v t j , junction temperature ( c) 125 100 75 50 25 0 ?25 80 i leak , leakage current ( a) 60 40 20 0
ncp1201 http://onsemi.com 8 typical characteristics figure 15. default current setpoint for skip cycle vs. junction temperature figure 16. propagation delay from current detection to gate driver vs. junction temperature figure 17. leading edge blanking duration vs. junction temperature figure 18. oscillator frequency vs. junction temperature figure 19. frequency jittering vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 100 t del , propagation delay (ns) 85 55 40 10 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 400 t leb , leading edge blanking duration (ns) 250 100 0 50 300 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 120 f osc , oscillator frequency (khz) 100 40 0 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 1400 f jitter , frequency jitter (hz/v) 800 600 200 0 400 60 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 85 d max , maximum duty cycle (%) 84 82 80 79 83 20 81 70 25 150 200 350 figure 20. maximum duty cycle vs. junction temperature 80 100 khz 60 khz 1200 1000 100 khz 60 khz t j , junction temperature ( c) 125 100 75 50 25 0 ?25 340 v ilskip , default current sense threshold for skip cycle (mv) 320 310 290 300 330
ncp1201 http://onsemi.com 9 typical characteristics figure 21. fb pin pullup resistor vs. junction temperature figure 22. feedback pin to pin 3 current setpoint ratio vs. junction temperature figure 23. bok threshold voltage vs. junction temperature figure 24. bok input bias current vs. junction temperature figure 25. bok source bias current vs. junction temperature figure 26. skip mode threshold voltage vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 1.15 v skip , skip cycle comparator threshold voltage (v) 1.10 1.05 1.00 0.95 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 19 r up , internal pullup resistor (k ) 18 16 13 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 51 i sc , bok bias current ( a) 50 49 46 45 47 17 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 2.00 v th , bok input threshold voltage (v) 1.95 1.85 1.75 1.70 t j , junction temperature ( c) 125 100 75 50 25 0 ?25 12 i ib?bok , bok input bias current (na) 9 8 7 6 10 1.90 15 14 11 48 v bok < v th 1.80 v bok < v th t j , junction temperature ( c) 125 100 75 50 25 0 ?25 3.40 i ratio , feedback pin to pin 3 current ratio 3.20 3.10 3.05 3.00 3.30 3.15 3.25 3.35
ncp1201 http://onsemi.com 10 detailed operating description introduction the ncp1201 implements a standard current mode architecture where the switch?off time is dictated by the peak current setpoint. this component represents the ideal candidate where low part?count is the key criteria, particularly in low?cost ac?dc adapters, auxiliary supplies etc. due to its high?performance high?voltage technology, the ncp1201 incorporates all the necessary components normally needed in uc384x based supplies: timing components, feedback devices, low?pass filter and self?supply. this later point emphasizes the fact that on semiconductor's ncp1201 does not need an auxiliary winding to operate: the device is self supplied from the high?voltage rail and delivers a v cc to the ic. this system is named the dynamic self?supply (dss). dynamic self?supply the dss principle is based on the char ge/discharge of the v cc bulk capacitor from a low level up to a higher level. we can easily describe the current source operation following simple logic equations: power?on: if v cc < v ccoff then current source is on, no output pulses if vcc decreasing > v ccon then current source is off, output is pulsing if vcc increasing < v ccoff then current source is on, output is pulsing typical values are: v ccoff = 12.5 v, v ccon = 10.5 v to better understand the operation principle, figure 27 sketch offers the necessary explanation, figure 27. the charge/discharge cycle over a 10 f v cc capacitor 10 ms 30 ms 50 ms 70 ms 90 ms current source off v cc output pulses vripple = 2 v vcc off = 12.5 v vcc on = 10.5 v on the dss behavior actually depends on the internal ic consumption and the mosfet's gate charge qg. if we select a mosfet like the mtp2n60e, qg max equals 22 nc. with a maximum switching frequency of 70 khz for the oscillator 60 khz, the average power necessary to drive the mosfet (excluding the driver efficiency and neglecting various voltage drops) is: p driver f sw(max) q g v cc (eq. 1) where, p driver = average power to drive the mosfet f sw(max) = maximum switching frequency qg = mosfet's gate charge v cc = vgs level applied to the gate of the mosfet to obtain an estimation of the driving current, simply divide pdriver by v cc , i driver f sw(max) q g 1.54 ma (eq. 2) the total standby power consumption at no?load will therefore heavily rely on the internal ic current consumption plus the driving current (altered by the driver's efficiency). suppose that the ic is supplied from a 350 vdc line. the current flowing through pin 8 is a direct image of the ncp1201 current consumption (neglecting the switching losses of the hv current source). if i cc2 equals 2.1 ma @ t a = 25 c, then the power dissipated (lost) by the ic is simply: 350 v x 2.1 ma = 735 mw. for design and reliability reasons, it would be interesting to reduce this source of wasted power. in order to achieve that, different methods can be used. 1. use a mosfet with lower gate charge qg; 2. connect pin through a diode (1n4007 typically) to one of the mains input. the average value on pin 8 becomes: v mainspeak 2 (eq. 3)
ncp1201 http://onsemi.com 11 our power contribution example drops to 223 v x 2.1 ma = 468.3 mw. if a resistor is installed between the mains and the diode, you further force the dissipation to migrate from the package to the resistor. the resistor value should be carefully selected to account for low?line startup. 1 2 3 4 8 7 6 5 figure 28. a simple diode naturally reduces the average voltage on pin 8 mains hv cbulk 3. permanently force the v cc level above vcc off with an auxiliary winding. it will automatically disconnect the internal startup source and the ic will be fully self?supplied from this winding. again, the total power drawn from the mains will significantly decrease. by using this approach, user need to make sure the auxiliary voltage never exceeds the 16 v limit for all line conditions. skipping cycle mode the ncp1201 automatically skips switching cycles when the output power demand drops below a preset level. this is accomplished by monitoring the fb pin. in normal operation, fb pin imposes a peak current according to the load value. if the load demand decreases, the internal loop asks for less peak current. when this set?point reaches the skip mode threshold level, 1.07 v, the ic prevents the current from decreasing further down and starts to blank the output pulses, i.e. the controller enters the so?called skip cycle mode, also named controlled burst operation. the power transfer now depends upon the width of the pulse bunches, figure 29. suppose we have the following component values: lp , primary inductance = 1.0 mh f sw , switching frequency = 60 khz i p (skip) = 200 ma (or 333 mv/r sense ) the theoretical power transfer is therefore: 1 2 l p i p 2 f sw 1.2 w (eq. 4) if the controller enters skip cycle mode with a pulse packet length of 20 ms over a recurrent period of 100 ms, then the total power transfer reduced to 1.2 w x 0.2 = 240 mw. to better understand how this skip cycle mode takes place, a look at the operation mode versus the fb pin voltage level shown below, immediately gives the necessary insight. 1.07 v 4.2 v, fb pin open fb normal current mode operation skip cycle operation i p(min) = 333 mv / r sense figure 29. feedback pin voltage and modes of operation 2.97 v, upper dynamic range when fb pin voltage level is above the skip cycle threshold (1.07 v by default), the peak current cannot exceed 0.9 v/r sense . when the ic enters the skip cycle mode, the peak current cannot go below v skip /3.3. by using the peak current limit reduction scheme, the skip cycle takes place at a lower peak current, which guarantees noise free operation.
ncp1201 http://onsemi.com 12 figure 30. mosfet v ds at various power levels, p1 ncp1201 http://onsemi.com 13 brownout detect protection in order to avoid output voltage bouncing during electricity brownout, a bulk capacitor voltage comparator with programmable hysteresis is included in this device. the non?inverting input, pin 1, is connected to the voltage divider comprised of r upper and r lower as shown in figure 32, monitoring the bulk capacitor voltage level. the inverting input is connected to a threshold voltage of 1.92 v internally. as bulk capacitor voltage drops below the pre?programmed level, i.e. pin 1 voltage drops below 1.92 v, a reset signal will be generated via internal protection logic to the pwm latch to turn off the power switch immediately. at the same time, an internal current source controlled by the state of the comparator provides a mean to setup the voltage hysteresis through injecting current into r lower . the equations below (equations 5 and 6) show the relationship between v bulk levels and the voltage divider network resistors. equations for resistors selection are: r upper r lower (v bulk_h v bulk_l ) 50 a (eq. 5) r lower [1.92 v(v bulk_h v bulk_l )] (50 a v bulk_h ) (eq. 6) assume v bulk_h = 90 vdc and v bulk_l = 80 vdc, by using 4.3 k for r lower then r upper is about 195.7 k . figure 32. brown?out protection operation r upper v bulk r lower bok v ref 50 a + 1.92 v uvlo ?
ncp1201 http://onsemi.com 14 application information power dissipation the ncp1201 can be directly supplied from the dc rail through the internal dss circuitry. the average current flowing through the dss is therefore the direct image of the ncp1201 current consumption. the total power dissipation can be evaluated using: (v hvdc 11 v) i cc2 . if the device operates on a 250 vac rail, the maximum rectified voltage can go up to 350 vdc. at t a = 25 c, i cc2 = 2.1 ma for the 60 khz version over a 1.0 nf capacitive load. as a result, the ncp1201 will dissipate 350 v x 2.1 ma = 735 mw (t a = 25 c). the soic?8 package offers a junction?to?ambient thermal resistance r j?a of 178 c/w. adding some copper area around the device pins will help to improve this number, 12mm x 12mm copper can drop r j?a down to 100 c/w with 35 copper thickness (1 oz.) or 6.5mm x 6.5mm with 70 copper thickness (2 oz.). with this later number, we can compute the maximum power dissipation the package accepts at an ambient of 50 c: p max t jmax ?t amax r j?a 750 mw (t jmax = 125 c), which is acceptable with our previous thermal budget. for the dip8 package, adding a min?pad area of 80mm 2 of 35 copper (1 oz.), r j?a drops from 100 c/w to about 75 c/w. in the above calculations, i cc2 is based on a 1.0 nf output capacitor. as seen before, i cc2 will depend on your mosfet's q g which i cc2 i cc1 + f sw x q g . final calculation should thus account for the total gate?charge q g your mosfet will exhibit. if the power estimation is beyond the limit, supply to the v cc with a series diode as suggested in figure 28 can be used. as a result, it will drop the average input voltage and lower the dissipation to 350 v 2 1.6 ma 356.5 mw . alternatively, an auxiliary winding can be used to disable the dss and hence reduce the power consumption down to v cc x i cc2 . by using the auxiliary winding supply method, the rectified auxiliary voltage should permanently stays above the v ccoff threshold voltage, keeping dss off and is safely kept well below the 16 v maximum rating for whole operating conditions. non?latching shutdown in some cases, it might be desirable to shut off the device temporarily and authorize its restart once the control signal has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb pin voltage below the v skip level, the output pulses are disabled as long as fb pin voltage is pulled below the skip mode threshold voltage. as soon as fb pin is released, the the device resumes its normal operation again. figure 33 depicts an application example. figure 33. a method to shut down the device without a definitive latchoff state on/off q1 8 7 6 5 1 2 3 4 fault protection in applications where the output current is purposely not controlled (e.g. wall adapters delivering raw dc level), it is often required to permanently latchoff the power supply in presence of a fault. this fault can be either a short?circuit on the output or a broken optocoupler. in this later case, it is important to quickly react in order to avoid a lethal output voltage runaway. the ncp1201 includes a circuitry tailored to tackle both events. a short?circuit forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler led. as a result, the fb pin level is pulled up to 4.2 v, as internally imposed by the ic. the peak current set?point goes to the maximum and the supply delivers a rather high power with all the associated effects. however, this can also happen in case of feedback loss, e.g. a broken optocoupler. to account for those situations, ncp1201 included a dedicated overload protection circuitry. once the protection activated, the circuitry permanently stops the pulses while the v cc moves between 10?12 v to maintain this latchoff state. the system resets when the user purposely cycles the v cc down below 3.0 v, e.g. when the power plug is removed from the mains. in ncp1201, the controller stops all output pulses as soon as the error flag is asserted, irrespective to the v cc level. however, to avoid false triggers during the startup sequence, ncp1201 purposely omits the very first v cc descent from 12 to 10 v. the error circuitry is actually armed just after this sequence, e.g. v cc crossing 10 v. figure 34 details the timing sequence. the v cc capacitor should be calculated carefully to of fer a sufficient time out during the first startup v cc descent.
ncp1201 http://onsemi.com 15 as shown below, the fault logic is armed once v cc crosses 10 v after startup phase. when powering the device from an auxiliary winding, meeting this condition can sometimes be problematic since upon startup, v cc naturally goes up and not down as with a dss. as a result, v cc never crosses 10 v and the fault logic is not activated. if a short?circuit takes place, the fault circuitry activates as soon as v cc collapses below 10 v (because of the coupling between v aux and v out ), but in presence of a broken optocoupler, i.e. feedback is open, v cc increases and the fault will never triggered! to avoid this problem, the application note atips and tricks with ncp1200, an8069/do offers some possible solutions where the dss is kept for protection logic operation only but all the driving power is derived from the auxiliary winding. some solutions even offer the ability to disable the dss in standby and benefit to low standby power. figure 34. fault protection timing diagram regulation occurs here overload is not activated overload is activated driver pulses latched?off fault occurs here regulation open?loop fb level v cc 12 v 10 v no synchronization between dss and fault event time time time drv fb calculating the v cc capacitor as the above section describes, the fall down sequence depends upon the v cc level, i.e. how long does it take for the v cc line to decrease from 12.5 v to 10.5 v. the required time depends on the powerup sequence of your system, i.e. when you first apply the power to the device. the corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12.5 v to 10.5 v, otherwise the supply will not properly startup. the test consists in either simulating or measuring in the laboratory to determine time required for the system to reach the regulation at full load. let's assume that this time corresponds to 6.0 ms. therefore a v cc fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. if the corresponding ic consumption, including the mosfet drive, establishes at 1.8 ma for instance, we can calculate the required capacitor using the following formula: t v c i , with v = 2.0 v. then for a wanted t of 10 ms, c equals 9.0 f or 10 f for a standard value. when an overload condition occurs, the ic blocks its internal circuitry and its consumption drops to 575 a typical. this explains the v cc falling slope changes after latchoff in figure 34.
ncp1201 http://onsemi.com 16 protecting the controller against negative spikes as with any controller built upon a cmos technology, it is the designer's duty to avoid the presence of negative spikes on sensitive pins. negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. sometimes, the injection can be so strong that internal parasitic scrs are triggered, engendering irremediable damages to the ic if they are a low impedance path is offered between v cc and gnd. if the current sense pin is often the seat of such spurious signals, the high?voltage pin can also be the source of problems in certain circumstances. during the turn?off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its v cc capacitor and keeps activating the mosfet on and off with a peak current limited by rsense. unfortunately, if the quality coefficient q of the resonating network formed by lp and cbulk is low (e.g. the mosfet rdson + rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. since we are talking about ms pulses, the amount of injected charge (q = i x t) immediately latches the controller which brutally discharges its v cc capacitor. if this v cc capacitor is of sufficient value, its stored energy damages the controller. figure 35 depicts a typical negative shot occurring on the hv pin where the brutal v cc discharge testifies for latchup. figure 35. a negative spike takes place on the bulk capacitor at the switch?off sequence simple and inexpensive cures exist to prevent from internal parasitic scr activation. one of them consists in inserting a resistor in series with the high?voltage pin to keep the negative current to the lowest when the bulk becomes negative (figure 36). please note that the negative spike is clamped to 2 x vf due to the diode bridge. please refer to and8069 for power dissipation calculations. another option (figure 37) consists in wiring a diode from v cc to the bulk capacitor to force v cc to reach uvlolow sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. for security reasons, two diodes can be connected in series. figure 36. a simple resistor in series avoids any latchup in the controller cv cc d3 1n4007 8 7 6 5 1 2 3 4 + cbulk + 1 3 cv cc rbulk > 4.7 k 8 7 6 5 1 2 3 4 + cbulk + 1 2 3 figure 37. or a diode forces v cc to reach uvlolow sooner
ncp1201 http://onsemi.com 17 ordering information device package shipping 2 ncp1201p60 pdip?8 50 units / rail ncp1201d60r2 soic?8 2500 units / reel NCP1201D60R2G soic?8 (pb?free) 2500 units / reel ncp1201p100 pdip?8 50 units / rail ncp1201p100g pdip?8 (pb?free) 50 units / rail ncp1201d100r2 soic?8 2500 units / reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1201 http://onsemi.com 18 package dimensions soic?8 d suffix case 751?07 issue ac *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1
ncp1201 http://onsemi.com 19 package dimensions pdip?8 p suffix case 626?05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ?a? ?b? ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040
ncp1201 http://onsemi.com 20 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp1201/d the product described herein (ncp1201), may be covered by the following u.s. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,70 9, 6,587,357. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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